/**
 @file sys_usw_interrupt_isr.c

 @date 2012-11-01

 @version v2.0

*/

/****************************************************************************
 *
* Header Files
*
****************************************************************************/
#include "ctc_error.h"
#include "ctc_macro.h"
#include "ctc_interrupt.h"

#include "sys_usw_common.h"
#include "sys_usw_interrupt.h"
#include "sys_usw_interrupt_priv.h"
#include "drv_api.h"

/****************************************************************************
 *
* Defines and Macros
*
*****************************************************************************/

/****************************************************************************
 *
* Global and Declaration
*
*****************************************************************************/
int32 _sys_usw_intr_log_normal_intr(uint8 lchip, sys_intr_abnormal_log_t log_intr)
{
    uint8 loop1 = 0;
    uint8 position = 0xFF;
    sys_intr_abnormal_log_t* p_log_intr;
    for(loop1=0; loop1 < SYS_INTR_LOG_NUMS; loop1++)
    {
        p_log_intr = p_usw_intr_master[lchip]->log_intr+loop1;
        if(p_log_intr->count && (log_intr.intr == p_log_intr->intr && log_intr.sub_intr == p_log_intr->sub_intr &&
            log_intr.low_intr == p_log_intr->low_intr && log_intr.real_intr == p_log_intr->real_intr))
        {
            position = loop1;
            break;
        }
        else if( (0 == p_log_intr->count) && position == 0xFF)
        {
            position = loop1;
        }
    }

    if(0xFF == position)
    {
        position = p_usw_intr_master[lchip]->oldest_log;
        sal_memset(&p_usw_intr_master[lchip]->log_intr[p_usw_intr_master[lchip]->oldest_log], 0, sizeof(sys_intr_abnormal_log_t));
        p_usw_intr_master[lchip]->oldest_log++;
        if(p_usw_intr_master[lchip]->oldest_log >= SYS_INTR_LOG_NUMS)
        {
            p_usw_intr_master[lchip]->oldest_log=0;
        }
    }


    p_usw_intr_master[lchip]->log_intr[position].intr = log_intr.intr;
    p_usw_intr_master[lchip]->log_intr[position].sub_intr = log_intr.sub_intr;
    p_usw_intr_master[lchip]->log_intr[position].low_intr = log_intr.low_intr;
    p_usw_intr_master[lchip]->log_intr[position].real_intr = log_intr.real_intr;
    p_usw_intr_master[lchip]->log_intr[position].count++;
    sal_time(&(p_usw_intr_master[lchip]->log_intr[position].last_time));

    return CTC_E_NONE;
}

/**
 @brief handle sup fatal interrupt
*/
int32
sys_usw_intr_isr_sup_fatal(uint8 lchip, uint32 intr, void* p_data)
{
    uint32* p_sup_fatal = p_data;   /* gb_sup_interrupt_fatal_t */
    sys_intr_type_t type;
    uint32 idx = 0;
    uint32 offset = 0;
    uint32 i = 0, j = 0, p = 0;
    uint32 sub_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32 low_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32 end_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint8  gchip = 0;
    ctc_interrupt_abnormal_status_t abnormal_status;
    ctc_intr_status_t* p_status = &(abnormal_status.status);
    int32 ret = CTC_E_NONE;
    uint8  action_type = 0;
    uint8 ecc_or_parity = 0;

    tbls_id_t intr_tbl = MaxTblId_t;
    uint16 k=0;

    sal_memset(&abnormal_status, 0, sizeof(abnormal_status));
    sal_memset(&type, 0, sizeof(sys_intr_type_t));
    type.intr = SYS_INTR_CHIP_FATAL;
    type.core_id = ((lchip - SYS_PP_BASE(lchip)) >= PP_NUM_PER_CORE) ? 1 : 0;
    abnormal_status.type.intr = CTC_INTR_CHIP_FATAL;

    /* 2. get & clear sub interrupt status */
    for (i = 0; i < p_usw_intr_master[lchip]->fatal_sub_cnt; i++)
    {
        idx = i / CTC_UINT32_BITS;
        offset = i % CTC_UINT32_BITS;

        if (0 == p_sup_fatal[idx])
        {
            /* bypass 32Bit 0 */
            i = (idx + 1) * CTC_UINT32_BITS-1;
            continue;
        }

        if (!CTC_IS_BIT_SET(p_sup_fatal[idx], offset))
        {
            continue;
        }
        type.sub_intr = i;
        type.low_intr = INVG;
        type.lvl4_intr = INVG;

        /* get sub interrupt status */
        _sys_usw_interrupt_get_status_fatal(lchip, &type, sub_bmp);

        if (!sub_bmp[0] && !sub_bmp[1] && !sub_bmp[2])
        {
            continue;
        }

        for (j = 0; j < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; j++)
        {
            if(!CTC_BMP_ISSET(sub_bmp, j))
            {
                continue;
            }

            sal_memset(low_bmp, 0, sizeof(low_bmp));
            type.low_intr = j;
            abnormal_status.type.sub_intr = i;
            abnormal_status.type.low_intr = j;

            SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "sup-intr:%d sub-intr:%d low-intr:%d\n",type.intr,type.sub_intr,type.low_intr);

            /*get low interrupt status*/
            ret = _sys_usw_interrupt_get_status_fatal(lchip, &type,low_bmp);
            if (ret < 0)
            {
                continue;
            }

            if(low_bmp[0] || low_bmp[1] || low_bmp[2] || low_bmp[3] || low_bmp[4] || low_bmp[5])
            {
                /* process all low interrupt*/
                for(k=0;k<CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; k++)
                {
                    if(!CTC_BMP_ISSET(low_bmp, k))
                    {
                        continue;
                    }

                    sal_memset(end_bmp, 0, sizeof(end_bmp));

                    if (DRV_FROM_AT(lchip))
                    {
                        type.lvl4_intr = k;

                        /*get end interrupt status*/
                        ret = _sys_usw_interrupt_get_status_fatal(lchip, &type, end_bmp);
                        if (ret < 0)
                        {
                            continue;
                        }
                    }


                    if (end_bmp[0] || end_bmp[1] || end_bmp[2] || end_bmp[3] || end_bmp[4] || end_bmp[5])
                    {
                        /* process all end interrupt */
                        for (p = 0; p < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; p++)
                        {
                            if (!CTC_BMP_ISSET(end_bmp, p))
                            {
                                continue;
                            }

                            /* real interrupt source */
                            sys_usw_interrupt_get_info(lchip, &type, p, &intr_tbl, &action_type, &ecc_or_parity);

                            if ( ecc_or_parity)
                            {
                                /* function interrupt for process ecc or parity */
                                sys_usw_interrupt_proc_ecc_or_parity(lchip, intr_tbl, p, abnormal_status.type);
                            }
                            else if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
                            {
                                SYS_USW_INTR_ABNORMAL_LOG_PROCESS(lchip, CTC_INTR_CHIP_FATAL, i, j, end_bmp);
                                ret = sys_usw_get_gchip_id(lchip, &gchip);
                                if (0 == ret)
                                {
                                    abnormal_status.type.intr = CTC_INTR_CHIP_FATAL;
                                    abnormal_status.type.sub_intr = i;
                                    sal_memcpy(p_status->bmp, end_bmp, sizeof(uint32)*CTC_INTR_STAT_SIZE);
                                    abnormal_status.type.low_intr = j;
                                    abnormal_status.type.lvl4_intr = k;
                                    abnormal_status.action = action_type? action_type: CTC_INTERRUPT_FATAL_INTR_RESET;
                                    p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, &abnormal_status);
                                }
                            }
                        }

                        /* clear end interrupt status in one time */
                        CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_fatal(lchip, &type, end_bmp));
                    }
                    else
                    {
                        /* no end table id, both arctic and tm2 will go here */
                        sys_usw_interrupt_get_info(lchip, &type, k, &intr_tbl, &action_type, &ecc_or_parity);

                        if ( ecc_or_parity)
                        {
                            /* function interrupt for process ecc or parity */
                            sys_usw_interrupt_proc_ecc_or_parity(lchip, intr_tbl, k, abnormal_status.type);
                        }
                        else if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
                        {
                            SYS_USW_INTR_ABNORMAL_LOG_PROCESS(lchip, CTC_INTR_CHIP_FATAL, i, j, low_bmp);
                            ret = sys_usw_get_gchip_id(lchip, &gchip);
                            if (0 == ret)
                            {
                                abnormal_status.type.intr = CTC_INTR_CHIP_FATAL;
                                abnormal_status.type.sub_intr = i;
                                sal_memcpy(p_status->bmp, low_bmp, sizeof(uint32)*CTC_INTR_STAT_SIZE);
                                abnormal_status.type.low_intr = j;
                                abnormal_status.action = action_type? action_type: CTC_INTERRUPT_FATAL_INTR_RESET;
                                p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, &abnormal_status);
                            }
                        }
                    }
                }

                type.lvl4_intr = INVG;
                /* clear low interrupt status in one time */
                CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_fatal(lchip, &type, low_bmp));
            }
            else
            {
                /* no low table id */
                sys_usw_interrupt_get_info(lchip, &type, j, &intr_tbl, &action_type, &ecc_or_parity);

                if ( ecc_or_parity)
                {
                    /* function interrupt for process ecc or parity */
                    sys_usw_interrupt_proc_ecc_or_parity(lchip, intr_tbl, j, abnormal_status.type);
                }
                else if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
                {
                    SYS_USW_INTR_ABNORMAL_LOG_PROCESS(lchip, CTC_INTR_CHIP_FATAL,i,j,low_bmp);
                    ret = sys_usw_get_gchip_id(lchip, &gchip);
                    if (0 == ret)
                    {
                        abnormal_status.type.intr = CTC_INTR_CHIP_FATAL;
                        abnormal_status.type.sub_intr = i;
                        abnormal_status.type.low_intr = j;
                        abnormal_status.action = action_type? action_type: CTC_INTERRUPT_FATAL_INTR_RESET;
                        p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, &abnormal_status);
                    }
                }
            }
        }
        /*clear sub interrup status*/
        type.low_intr = INVG;
        CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_fatal(lchip, &type, sub_bmp));
    }

    return CTC_E_NONE;
}

/**
 @brief handle sup normal interrupt
*/
int32
sys_usw_intr_isr_sup_normal(uint8 lchip, uint32 intr, void* p_data)
{
    if (MCHIP_INTR(lchip)->intrrupt_isr_sup_normal)
    {
        MCHIP_INTR(lchip)->intrrupt_isr_sup_normal(lchip, intr, p_data);
    }

    return CTC_E_NONE;
}

int32
sys_usw_intr_isr_pcie(uint8 lchip, uint32 intr, void* p_data)
{
    SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "pcie error!, bmp = 0x%x\n", *((uint32*)p_data));
    return CTC_E_NONE;
}

/*
  Flexe event isr cb function
*/
STATIC int32
sys_usw_flexe_isr(uint8 lchip, uint32 intr, void* p_data)
{
    uint8 flexe_shim_id = 0;
    uint32 cmd = 0;
    FlexeMgrInterruptFunc_m flexemgr_intr;
    uint32 index = 0;

    /*1. decode flexe intr to identify real event to process */
    if ((SYS_INTR_FUNC_FLEX_DP0 == intr) || (SYS_INTR_FUNC_FLEX_DP1 == intr))
    {
        flexe_shim_id = (intr - SYS_INTR_FUNC_FLEX_DP0);
        cmd = DRV_IOR(FlexeMgrInterruptFunc_t, DRV_ENTRY_FLAG);
        index = DRV_INS(flexe_shim_id, 0);
        DRV_IOCTL(lchip, index, cmd, &flexemgr_intr);
        if (GetFlexeMgrInterruptFunc(V, funcIntrFlexeTsCaptureAvail_f, &flexemgr_intr))
        {
            p_usw_intr_master[lchip]->flexe_cb[SYS_INTR_FLEXE_SUB_TYPE_PTP](lchip, intr, p_data);
        }
        p_usw_intr_master[lchip]->flexe_cb[SYS_INTR_FLEXE_SUB_TYPE_OH](lchip, intr, p_data);
    }
    else if (SYS_INTR_CHIP_NORMAL == intr)
    {
        p_usw_intr_master[lchip]->flexe_cb[SYS_INTR_FLEXE_SUB_TYPE_OH](lchip, intr, p_data);
    }

    return CTC_E_NONE;
}

/* default interrupt configuration */
sys_intr_mapping_t sys_usw_intr_default[] =
{
    {0,    SYS_INTR_CHIP_FATAL,                     "Chip Fatal",             NULL},
    {0,    SYS_INTR_CHIP_NORMAL,                    "Chip Normal",            NULL},
    {0,    SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO,        "PTP Ts Capture",    NULL},
    {0,    SYS_INTR_FUNC_PTP_TOD_PULSE_IN,           "PTP TOD Pulse In",       NULL},
    {0,    SYS_INTR_FUNC_PTP_TOD_CODE_IN_RDY,       "PTP TOD Code Ready",  NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_PULSE_IN,       "PTP Sync Pulse In",     NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY,   "PTP Sync Code Ready",    NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_CODE_IN_ACC,   "PTP Sync Code ACC",      NULL},
    {0,    SYS_INTR_FUNC_STATS_STATUS_ADDR,      "Statistics ",         NULL},
    {0,    SYS_INTR_FUNC_MET_LINK_SCAN_DONE,     "HW Based APS Failover",  NULL},
    {0,    SYS_INTR_FUNC_MDIO_CHANGE_0,          "MDIO Change 0",         NULL},
    {0,    SYS_INTR_FUNC_MDIO_CHANGE_1,          "MDIO Change 1",         NULL},
    {0,    SYS_INTR_FUNC_CHAN_LINKDOWN_SCAN,     "Chan Link Scan",              NULL},
    {0,    SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW,  "IPfix Useage",         NULL},
    {0,    SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO,  "Fib Acc Learning FIFO",         NULL},
    {0,    SYS_INTR_FUNC_OAM_DEFECT_CACHE,       "OAM Defect",           NULL},

    {0,    SYS_INTR_FUNC_BSR_C2C_PKT_CONGESTION,       "BSR C2C Packet Congestion",           NULL},
    {0,    SYS_INTR_FUNC_BSR_TOTAL_CONGESTION,         "BSR Total Packet Congestion",           NULL},
    {0,    SYS_INTR_FUNC_BSR_OAM_CONGESTION,           "BSR OAM Congestion",           NULL},
    {0,    SYS_INTR_FUNC_BSR_DMA_CONGESTION,           "BSR DMA Congestion",           NULL},
    {0,    SYS_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION,  "BSR Critical Packet Congestion",           NULL},
    {INVG,    SYS_INTR_FUNC_OAM_AUTO_GEN,                 "OAM Auto Gen",           NULL},

    {0,    SYS_INTR_PCS_LINK_31_0,               "MAC PCS Link 0",         NULL},
    {0,    SYS_INTR_PCS_LINK_47_32,              "MAC PCS Link 1",         NULL},

    {0,    SYS_INTR_FUNC_MDIO_XG_CHANGE_0,          "MDIO XG Change 0",         NULL},
    {0,    SYS_INTR_FUNC_MDIO_XG_CHANGE_1,          "MDIO XG Change 1",         NULL},
    {0,    SYS_INTR_PCIE_BURST_DONE,             "PCIe Burst Done",      NULL},
    {0,    SYS_INTR_DMA,                       "DMA ",                NULL},
    {0,    SYS_INTR_MCU_SUP,                       "Mcu Sup Intr",                NULL},
    {0,    SYS_INTR_MCU_NET,                       "Mcu Net Intr ",                NULL},
    /* TsingMa */
    {0,    SYS_INTR_FUNC_STMCTL_STATE,             "Storm Control State",          NULL},
    {0,    SYS_INTR_FUNC_EPE_IPFIX_USEAGE_OVERFLOW,"EPE IPfix Useage",             NULL},
    {0,    SYS_INTR_GPIO,                          "GPIO",                         NULL},
    {0,    SYS_INTR_SOC_SYS,                       "Soc Sys",                      NULL},
    /* TsingMa.MX */
    {0,    SYS_INTR_FUNC_TCAM_SCAN_ERROR,            "Tcam Scan",                    NULL},
    {0,    SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR,   "Svc Policing",                 NULL},
    {0,    SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_0,       "DP1 MDIO XG Change 0",         NULL},
    {0,    SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_1,       "DP1 MDIO XG Change 1",         NULL},
    {0,    SYS_INTR_FUNC_SPN_DMA_DROPL,              "Spn Dma Drop Local Info",      NULL},
    {0,    SYS_INTR_FUNC_SPN_DMA_DROPM,              "Spn Dma Drop Master Info",     NULL},
    {0,    SYS_INTR_FUNC_SPN_CPU_REPORTL,            "Spn Cpu Report Local Info",    NULL},
    {0,    SYS_INTR_FUNC_SPN_CPU_REPORTM,            "Spn Cpu Report Master Info",   NULL},
    {0,    SYS_INTR_FUNC_CPU_MAC,                    "Cpu Mac",                      NULL},

    {0,    SYS_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION,       "DP1 BSR C2C Packet Congestion",         NULL},
    {0,    SYS_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION,         "DP1 BSR Total Packet Congestion",       NULL},
    {0,    SYS_INTR_FUNC_DP1_BSR_OAM_CONGESTION,           "DP1 BSR OAM Congestion",                NULL},
    {0,    SYS_INTR_FUNC_DP1_BSR_DMA_CONGESTION,           "DP1 BSR DMA Congestion",                NULL},
    {0,    SYS_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION,  "DP1 BSR Critical Packet Congestion",    NULL},

    {0,    SYS_INTR_FUNC_FLEX_DP0,                "FlexE DP0",                      sys_usw_flexe_isr},
    {0,    SYS_INTR_FUNC_FLEX_DP1,                "FlexE DP1",                      sys_usw_flexe_isr},
    {0,    SYS_INTR_FUNC_OMC_TR,                  "OMC TR",                      NULL},
    {0,    SYS_INTR_FUNC_OMC_TL,                  "OMC_TL",                      NULL},
    {0,    SYS_INTR_FUNC_OMC_BR,                  "OMC_BR",                      NULL},
    {0,    SYS_INTR_FUNC_OMC_BL,                  "OMC_BL",                      NULL},
    {0,    SYS_INTR_FUNC_DP0_MACSEC_RX,           "DP0 MACSEC RX",               NULL},
    {0,    SYS_INTR_FUNC_DP1_MACSEC_RX,           "DP1 MACSEC RX",               NULL},
    {0,    SYS_INTR_FUNC_DP0_MACSEC_TX,           "DP0 MACSEC TX",               NULL},
    {0,    SYS_INTR_FUNC_DP1_MACSEC_TX,           "DP1 MACSEC TX",               NULL},
    {0,    SYS_INTR_FUNC_DP0_MC_MAC0,             "DP0 MC MAC0",                 NULL},
    {0,    SYS_INTR_FUNC_DP0_MC_MAC1,             "DP0 MC MAC1",                 NULL},
    {0,    SYS_INTR_FUNC_DP0_MC_MAC2,             "DP0 MC MAC2",                 NULL},
    {0,    SYS_INTR_FUNC_DP0_MC_MAC3,             "DP0 MC MAC3",                 NULL},
    {0,    SYS_INTR_FUNC_DP1_MC_MAC0,             "DP1 MC MAC0",                 NULL},
    {0,    SYS_INTR_FUNC_DP1_MC_MAC1,             "DP1 MC MAC1",                 NULL},
    {0,    SYS_INTR_FUNC_DP1_MC_MAC2,             "DP1 MC MAC2",                 NULL},
    {0,    SYS_INTR_FUNC_DP1_MC_MAC3,             "DP1 MC MAC3",                 NULL},
    {0,    SYS_INTR_FUNC_PTP_TOD_PULSE,           "PTP TOD Pulse",                 NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_PULSE,         "PTP Sync Pulse",                 NULL},
    {0,    SYS_INTR_FUNC_FLEXE0_MCU_REQ,         "FlexE0 MCU Req",               NULL},
    {0,    SYS_INTR_FUNC_FLEXE1_MCU_REQ,         "FlexE1 MCU Req",               NULL},
    {0,    SYS_INTR_FUNC_MISC_MCU_REQ,            "Misc MCU Req",                  NULL},
    {0,    SYS_INTR_FUNC_ECPU,                        "Interrupt From ECPU",           NULL},
    {0,    SYS_INTR_FUNC_SCPU,                        "Interrupt From SCPU",           NULL},
    {0,    SYS_INTR_FUNC_MAC,                        "MC MAC",           NULL},
    {0,    SYS_INTR_FUNC_BSR_ERM_MON,                        "BSR ERM MON",           NULL},
    {0,    SYS_INTR_FUNC_BSR_IRM_MON,                        "BSR IRM MON",           NULL},
    {0,    SYS_INTR_FUNC_BSR_CONGESTION,                        "BSR Congestion",           NULL},
    {0,    SYS_INTR_FUNC_OAM_TWAMP,                        "OAM Twamp",           NULL},
    {0,    SYS_INTR_FUNC_MISC_EVENT,                        "Misc Event",           NULL},
    {0,    SYS_INTR_FUNC_MACSEC,                        "MacSec",           NULL},
    {0,    SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_1,                        "Statistics 1",           NULL},
    {0,    SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_2,                        "Statistics 2",           NULL},
    {0,    SYS_INTR_FUNC_STATS_STATUS_ADDR_SLICE_3,                        "Statistics 3",           NULL},
    {0,    SYS_INTR_FUNC_STMCTL_STATE_1,                        "Storm Control State 1",           NULL},
    {0,    SYS_INTR_FUNC_STMCTL_STATE_2,                        "Storm Control State 2",           NULL},
    {0,    SYS_INTR_FUNC_STMCTL_STATE_3,                        "Storm Control State 3",           NULL},
    {0,    SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_1,                        "Svc Policing 1",           NULL},
    {0,    SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_2,                        "Svc Policing 2",           NULL},
    {0,    SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR_3,                        "Svc Policing 3",           NULL},
    {0,    SYS_INTR_CPU_SUB_DECODE_0,                        "Decode 0",           NULL},
    {0,    SYS_INTR_CPU_SUB_DECODE_1,                        "Decode 1",           NULL},
    {0,    SYS_INTR_CPU_SUB_DECODE_2,                        "Decode 2",           NULL},
    {0,    SYS_INTR_CPU_SUB_DECODE_3,                        "Decode 3",           NULL},
    {0,    SYS_INTR_CPU_SUB_ECPU_00,                        "Interrupt From ECPU 0",           NULL},
    {0,    SYS_INTR_CPU_SUB_ECPU_01,                        "Interrupt From ECPU 1",           NULL},
    {0,    SYS_INTR_CPU_SUB_ECPU_10,                        "Interrupt From ECPU 2",           NULL},
    {0,    SYS_INTR_CPU_SUB_ECPU_11,                        "Interrupt From ECPU 3",           NULL},
    {0,    SYS_INTR_CPU_SUB_UART,                        "Interrupt From UART",           NULL},
    {0,    SYS_INTR_CPU_SUB_QSPI,                        "Interrupt From QSPI",           NULL},
    {0,    SYS_INTR_CPU_SUB_GPIO,                        "Interrupt From GPIO",           NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_PULSE1,                "PTP Sync pulse 1",           NULL},
    {0,    SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY1,          "PTP Sync Code Ready 1",           NULL},
    {0,    SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_START,          "PTP tx fifo 0 start",           NULL},
    {0, 103, "PTP tx fifo 0", NULL},
    {0, 104, "PTP tx fifo 0", NULL},
    {0, 105, "PTP tx fifo 0", NULL},
    {0, 106, "PTP tx fifo 0", NULL},
    {0, 107, "PTP tx fifo 0", NULL},
    {0, 108, "PTP tx fifo 0", NULL},
    {0, 109, "PTP tx fifo 0", NULL},
    {0, 110, "PTP tx fifo 0", NULL},
    {0, 111, "PTP tx fifo 0", NULL},
    {0, 112, "PTP tx fifo 0", NULL},
    {0, 113, "PTP tx fifo 0", NULL},
    {0, 114, "PTP tx fifo 0", NULL},
    {0, 115, "PTP tx fifo 0", NULL},
    {0, 116, "PTP tx fifo 0", NULL},
    {0, 117, "PTP tx fifo 0", NULL},
    {0, 118, "PTP tx fifo 0", NULL},
    {0, 119, "PTP tx fifo 0", NULL},
    {0, 120, "PTP tx fifo 0", NULL},
    {0,    SYS_INTR_FUNC_PTP_TX_TS_FIFO_0_END,          "PTP tx fifo 0 end",           NULL},
    {0,    SYS_INTR_FUNC_PTP_TX_TS_FIFO_1_START,          "PTP tx fifo 1 start",           NULL},

    {0, 123, "PTP tx fifo 1", NULL},
    {0, 124, "PTP tx fifo 1", NULL},
    {0, 125, "PTP tx fifo 1", NULL},
    {0, 126, "PTP tx fifo 1", NULL},
    {0, 127, "PTP tx fifo 1", NULL},
    {0, 128, "PTP tx fifo 1", NULL},
    {0, 129, "PTP tx fifo 1", NULL},
    {0, 130, "PTP tx fifo 1", NULL},
    {0, 131, "PTP tx fifo 1", NULL},
    {0, 132, "PTP tx fifo 1", NULL},
    {0, 133, "PTP tx fifo 1", NULL},
    {0, 134, "PTP tx fifo 1", NULL},
    {0, 135, "PTP tx fifo 1", NULL},
    {0, 136, "PTP tx fifo 1", NULL},
    {0, 137, "PTP tx fifo 1", NULL},
    {0, 138, "PTP tx fifo 1", NULL},
    {0, 139, "PTP tx fifo 1", NULL},
    {0, 140, "PTP tx fifo 1", NULL},

    {0,    SYS_INTR_FUNC_PTP_TX_TS_FIFO_1_END,          "PTP tx fifo 1 end",           NULL},
    {0,    SYS_INTR_FUNC_DP0_MC_MAC4,          "DP0 MC MAC4",           NULL},
    {0,    SYS_INTR_FUNC_DP1_MC_MAC4,          "DP1 MC MAC4",           NULL}
};

/* default interrupt group configuration, need to change the IRQ and priority of groups based on your requirement
 * the priority range is [1, 139] for linux, thereinto [1, 99] is realtime schedule; and [0, 255] for vxworks
 */
ctc_intr_group_t sys_usw_intr_group_default[] =
{
 /*-    {0, 16, SAL_TASK_PRIO_DEF,  "Function normal group"}    //for pin*/
    {0, 0, SAL_TASK_PRIO_DEF,  "Function normal group"}    /*for msi*/
};

/**
 @brief get default interrupt global configuration
*/
int32
sys_usw_interrupt_get_default_global_cfg(uint8 lchip, sys_intr_global_cfg_t* p_intr_cfg)
{
    uint32 group_count = 0;
    uint32 intr_count = 0;

    /* use default global configuration in sys */
    group_count = COUNTOF(sys_usw_intr_group_default);
    intr_count = COUNTOF(sys_usw_intr_default);
    if (group_count > SYS_USW_MAX_INTR_GROUP)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (intr_count > SYS_INTR_MAX)
    {
        return CTC_E_INVALID_PARAM;
    }

    p_intr_cfg->group_count = group_count;
    sal_memcpy(&(p_intr_cfg->group), sys_usw_intr_group_default, sizeof(sys_usw_intr_group_default));
    sal_memcpy(&(p_intr_cfg->intr), sys_usw_intr_default, sizeof(sys_usw_intr_default));
    p_intr_cfg->intr_mode  = 0;

    return CTC_E_NONE;
}

